TSMC is accelerating plans to bring a new advanced chip packaging technology called CoPoS into production by 2028, with Nvidia's next-generation AI chip — codenamed Feynman — serving as the apparent catalyst for the push.
According to an analyst report covered by Wccftech, Nvidia's Feynman chip is "poised to break the CoWoS size barrier." CoWoS — short for Chip-on-Wafer-on-Substrate — is the current advanced packaging approach TSMC uses to stack and connect chips in today's AI accelerators, including Nvidia's H100 and B200 series. The implication is that Feynman will be physically too large or too complex for CoWoS to handle.
CoPoS is positioned as the successor: a next-generation packaging method that GuruFocus describes as expected to "revolutionize chip packaging." Huawei Central notes that TSMC "could bring" the technology by 2028, reflecting some remaining uncertainty in the timeline.
Chip packaging has quietly become one of the central battlegrounds in the AI hardware race. Raw transistor performance is only part of the equation — how chips are physically connected and how much data can flow between them at low latency increasingly determines real-world AI training speed. Technologies like CoWoS are why Nvidia's GPUs can act as unified computing slabs despite being assembled from multiple separate dies.
If TSMC hits its 2028 target, CoPoS could allow Nvidia — and potentially other customers — to build AI chips at a scale that simply isn't possible today, extending the performance curve at a moment when demand for AI compute shows no signs of slowing.