The race to pack more computing power into a single chip package has a clear leader, at least according to TSMC. The world's dominant chipmaker says its CoWoS (Chip on Wafer on Substrate) technology remains far ahead of the rival panel-level packaging approach for building the largest, most powerful AI processors.
According to Tom's Hardware, TSMC's Kevin Zhang stated that wafer-level packaging is "considerably more advanced" than panel-level packaging. Zhang's comments underscore that while both approaches aim to stitch multiple chips together into one dense unit, they are not equals — at least not yet.
The numbers back up that confidence. According to Tom's Hardware, TSMC's wafer-level packaging can scale to accommodate as many as 58 massive dies in a single package — a staggering figure that reflects the insatiable appetite AI workloads have for raw compute.
That doesn't mean TSMC is ignoring panel-level packaging entirely. The company is actively exploring the technology and developing its own variant, called CoPoS. Panel packaging uses larger, flat substrates — more like circuit boards than silicon wafers — which could eventually make chip assembly cheaper and more flexible. But TSMC is signaling that CoPoS is a longer-term investment, not an imminent replacement for CoWoS.
For the AI industry, this matters enormously. The chips powering today's large language models and AI training clusters are pushing the limits of what conventional single-die manufacturing can deliver. Advanced packaging — stitching multiple chiplets together — has become one of the primary ways chipmakers keep performance scaling. TSMC's insistence that CoWoS leads the field suggests that companies building the next generation of AI hardware will continue to depend heavily on TSMC's most advanced packaging capabilities for years to come.