Two of the world's biggest chipmakers are laying out roadmaps that converge on the same year — 2029 — as the race to build faster, more efficient AI hardware intensifies.
According to Tech Times, Samsung has reaffirmed plans to begin producing 1.4-nanometer chips in 2029. The company is also adding an enhanced version of that technology, a node it calls SF1.4+. In chipmaking, a smaller nanometer figure generally signals the ability to pack more transistors into the same space, which can mean better performance and lower power use — both critical for the data centers that run AI models.
Meanwhile, DigiTimes reports that rival TSMC is accelerating work on a next-generation packaging technology called CoPoS, also targeting 2029. Rather than shrinking the chip itself, this approach changes how chips are assembled. TSMC is shifting from the round 12-inch wafers the industry has long relied on to a larger rectangular "panel-level" format measuring 310mm. Packaging — how individual chips are combined and connected — has become a key battleground in AI hardware, because moving to bigger panels can let manufacturers build larger, more powerful chip assemblies more efficiently.
The two efforts attack the same problem from different angles: Samsung is pushing the frontier of how small the transistors can get, while TSMC is rethinking the physical format in which finished chips are produced and combined.
Both roadmaps remain years out, and plans at this stage can shift as technical and market conditions change. Neither source detailed pricing or customer commitments.
Why it matters: the chips that power artificial intelligence depend on advances in both manufacturing and packaging, and these dueling 2029 targets show the industry's two leading foundries are betting heavily on the next leap in AI computing.