Chipmaking giant TSMC is speeding up work on a next-generation packaging technology called CoPoS, which is positioned to eventually replace its widely used CoWoS approach, according to Wccftech.
Packaging may sound like an afterthought, but in modern computing it is anything but. As individual chips approach their physical limits, the way multiple chips and components are stitched together into a single, high-performance unit has become one of the most important factors in building advanced processors — especially the kind that power artificial intelligence systems. CoWoS, TSMC's current method, has been a key enabler of that work.
The shift to CoPoS centers on the use of glass core substrates. According to Wccftech, these glass cores cut costs by 30% and push wafer utilization past 90%. In plain terms, wafer utilization measures how much usable product TSMC can squeeze out of each silicon wafer. Getting that figure above 90% means less waste and more finished output from the same starting material — a meaningful efficiency gain in a business where every wafer is expensive.
The combination of lower costs and higher utilization is the headline benefit. If TSMC can produce more advanced packages for less money, that has ripple effects across the companies that depend on its manufacturing, from AI accelerator designers to the broader electronics supply chain.
The source frames CoPoS as an acceleration of an existing roadmap rather than a sudden pivot, with the glass-core technology driving the economics that make the transition attractive.
Why it matters: TSMC sits at the heart of the global chip supply chain, so a cheaper, more efficient packaging method could lower the cost and expand the supply of the advanced processors that power AI and modern electronics.