IBM has developed a chip built on sub-1 nanometer technology that stacks its transistors vertically, in three dimensions, with artificial intelligence workloads as the target, according to a report from Memeburn carried via Google News.
The two ideas in that description are what make the news notable. "Sub-1 nanometer" refers to an extremely small manufacturing scale — the dimension used as shorthand for how tightly a chip's building blocks are packed. The smaller that figure, the more transistors a chip can hold in the same space. "Stacking transistors in 3D" means arranging those components in vertical layers rather than spreading them out flat on a single plane, which is the more familiar approach in conventional chip design.
Memeburn frames the work specifically around AI. Modern AI systems are demanding on hardware, and chipmakers have been racing to pack more computing power into each chip while managing heat and energy use. A design that combines a sub-1nm scale with 3D stacking points toward fitting more capability into a given footprint.
It's worth being clear about what this report does and does not establish. The available source is a single headline-level item attributed to Memeburn, so details such as performance figures, timelines, manufacturing partners, and when — or whether — such a chip might reach commercial production are not specified here. Readers should treat the announcement as an early signal of a research direction rather than a finished product on shelves.
Why it matters: if IBM's approach holds up beyond the lab, squeezing transistors into sub-1nm 3D stacks could help chipmakers keep boosting the raw power available for AI even as the traditional path of simply shrinking flat chips runs into physical limits.