The AI chip race has long been fought at the level of transistors and silicon design, but a quieter contest is heating up one layer above: how chips are packaged together. According to Spherical Insights, advanced chip packaging has become "the new frontline of the AI chip race," as the industry scrambles to squeeze more performance out of hardware by connecting chips more efficiently.
TSMC, the world's dominant chip manufacturer, is exploring a significant materials shift in its CoWoS packaging technology — a method used to bundle AI chips and memory into dense, high-performance units. According to Wccftech, TSMC is betting on glass substrates as a replacement for today's organic materials, citing thermal properties that more closely mimic silicon. The catch: mass production of glass-based CoWoS remains distant, meaning the technology is promising but not yet ready for the factory floor.
On the equipment side, Lam Research — a major supplier of chip-manufacturing tools — is projecting its packaging business to grow by 50%, according to The Globe and Mail, which describes the figure as a potential "hidden catalyst" for the company's financial performance. That kind of growth signals that the broader industry is pouring real money into packaging infrastructure, not just chip design.
The stakes are high because packaging has become a genuine performance bottleneck. As raw transistor scaling slows, the way chips communicate with each other inside a package increasingly determines how fast AI systems can train models and run inference. Whoever masters next-generation packaging — whether through materials like glass or new bonding techniques — gains a meaningful edge in the race to power AI at scale.